3D memories can be much lower cost than conventional 2D memories. If a conventional memory occupies A square millimeters of silicon area, then a 3D memory comprising N planes of bits occupies approximately (A/N) square millimeters of silicon area. Reduced area means that more finished memory devices can be built on a single wafer, thereby reducing cost. Thus there is a strong incentive to pursue 3D memories having many planes of memory cells.
Johnson U.S. Pat. No. 6,034,882, assigned to the assignee of the present invention and hereby incorporated by reference in its entirety, describes a 3-dimensional, field-programmable, non-volatile memory that is well suited to extremely small memory cells. Each memory cell includes a self-aligning pillar of layers formed at the intersection between upper and lower conductors. In one embodiment, each memory cell includes a steering element such as a diode that is connected in series with a state change element such as an anti-fuse layer. Each pillar is isolated from neighboring pillars by a pair of self-aligned etch steps and subsequent dielectric depositions. When the anti-fuse layer is intact (the cell is not programmed), the cell is electrically an open circuit. When the anti-fuse layer is breached (the cell is programmed), the cell is electrically a diode in series with the resistance of the breached anti-fuse layer. Unfortunately, the area and perimeter of this diode are the full area and full perimeter of the pillar, and so this diode""s leakage is relatively high.
Knall U.S. patent application Ser. No. 09/560,626 discloses a memory cell with low leakage. The disclosed memory cell places an anti-fuse layer between the anode and the cathode of the diode. When the anti-fuse layer is intact, the cell is electrically an open circuit. But when the anti-fuse is breached, the anode material and cathode material are bought together in a small-diameter filament, and a diode is formed. The small filament gives the so-formed diode a very small area and a very small perimeter. Thus the diode""s leakage is relatively low. This is advantageous in the construction of a memory, since diode leakage makes sensing (for read operations) difficult, and since diode leakage current increases power consumption.
Knall""s embodiments use a xe2x80x9crail stackxe2x80x9d configuration, in which the anode material and the cathode material are continuous stripes extending in orthogonal directions. These embodiments are fabricated with the following steps: deposit the rail stack materials, etch them into stripes, dielectric fill between them, and polish back to expose the top of the rail stack. Then the thin anti-fuse dielectric is deposited or grown. As will be appreciated by those skilled in the art, it is more difficult to form a high-quality, thin dielectric film if that film is to be created on a polished surface. The polish operation (conventionally carried out using a CMP, Chemical Mechanical Polish, process) creates defects and leaves particles of slurry behind. This makes it harder to create a high quality film.
A need presently exists for an improved memory that is characterized by small cell size, ease of manufacture, and low leakage.
By way of general introduction, the preferred embodiments described below include an array of pillars that are self-aligned at the intersection of first and second crossing conductors. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by an anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.
This section has been provided by way of general introduction, and it is not intended to narrow the scope of the following claims.